MONDAY, MAY 10
Please have lunch before arriving at the facility; lunch will not be served on the first day.
Registration & Check-In
1:00 p.m.- 6:00 p.m. Registration:
Pick up badges and handouts
1:00 p.m.- 10:00 p.m. Room check-in:
Get room assignment & room key
SEMINARS
1:25 p.m. - 1:30 p.m. Seminar Welcome
Horst Gieser, Seminar Chair
1:30 p.m. - 2:50 p.m. Seminar 1 - CDM and Alternatives
Heinrich Wolf, Fraunhofer IZM
3:00 p.m. - 4:20 p.m. Seminar 2 - EMI/EMC Design
4:20 p.m. - 4:50 p.m. BREAK (Refreshments Provided)
4:50 p.m. - 6:10 p.m. Seminar 3 - RF ESD incl. MEMS
6:30 p.m. - 8:00 p.m. DINNER (Dining Room)
8:00 p.m. - 9:20 p.m. Seminar 4 - ESD Aspects of FINFETs
Christian Russ, Infineon Technologies
TUESDAY, MAY 11
7:00 a.m. - 8:00 a.m. BREAKFAST (Dining Room)
8:00 a.m. - 8:20 a.m. Welcome & Announcements
8:20 a.m. - 9:20 a.m. Invited Keynote: Design of an ESD
Robust Wireless Sensor
Chip for Medical Applications
Paul Paddan, Toumaz Technology
Poster Session 1
9:20 a.m. - 9:30 a.m. Poster Session 1 Introduction
Natarajan Mahadeva Iyer, GLOBALFOUNDRIES
9:30 a.m. - 10:10 a.m. Poster Presentation Summaries
Poster 1.1 – Impact of Difference Between Discharge Methods on CDM ESD Testing Y. Morishita, H. Ishizuka, T. Hiraoka, K. Hashimoto, N. Wakai, S. Kumashiro, MIRAI-Selete
Poster 1.2 – Negative Effects of Air Discharge Suppression on Field- Induced CDM Test Repeatability David Eppes, Danielle Roth-Dunn, Mark Lapina, Warren Anderson, Advanced Micro Devices
Poster 1.3 – Exceptional First CDM Discharge Pulse Tilo Brodbeck, Reinhold Gaertner, Infineon Technologies
Poster 1.4 – Practical Approaches to CDM Test on High Speed and Large Package Devices Agha Jahanzeb, Charvaka Duvvury, Joe Schichl, James McGee, Texas Instruments; John Fox, Texas Instruments Limited
Poster 1.5 – ESD Evaluation of 3D SIC Technology Using TSV S. Thijs, D. Linten, A. Mercha, G. Van der Plas, Y. Travaly, J. Van Olmen, IMEC; M. Scholz, IMEC and Vrije Universitei; G. Groeseneken, IMEC and Katholieke Universiteit Leuven
Poster 1.6 – Electrical Pulse Stressed Film Resistive Structures D. Bonfert, H. Wolf, H. Gieser, G. Klink, K. Bock, Fraunhofer Institute Reliability and Microintegration
Poster 1.7 – An Integrated Measurement Set-Up to Study the Impact of Atmosphere on ESD in MEMS Sandeep Sangameswaran, Guido Groeseneken, IMEC, ESAT, Katholieke Universiteit Leuven; Jeroen De Coster, Vladimir Cherman, Dimitri Linten, Steven Thijs, IMEC; Mirko Scholz, IMEC, Vrije Universiteit Brussels; Ingrid De Wolf, IMEC, MTM, Katholieke Universiteit Leuven
Poster 1.8 – Experimental Study of Gated Diode as ESD Protection in FDSOI High-k/Metal Gate 45 nm Node Technology Thomas Benoist, STMicroelectronics Crolles, CEA-Leti Minatec, IMEP-LAHC, Grenoble INP, Minatec; Claire Fenouillet-Beranger, Pierre Perreau, STMicroelectronics Crolles, CEA-Leti Minatec; Philippe Galy, Blaise Jaquier, STMicroelectronics; Christel Buj, Olivier Faynot, CEA-Leti Minatec; Pierre Gentil, IMEP-LAHC, Grenoble INP, Minatec
10:10 a.m. - 10:25 a.m. Group Picture
10:25 a.m. - 12:00 p.m. Poster Session 1 (
Refreshments provided)
12:00 p.m. - 1:20 p.m. LUNCH (Dining Room)
Technical Session A - On-chip Protection Devices
1:20 p.m.- 1:25 p.m. Announcements
Gaudenzio Meneghesso, Technical Program Chair
1:25 p.m. - 1:50 p.m. Presentation A.1 – Insights into
Breakdown of
High-k/Metal Gate Stacks Under ESD Stress
A. Ille, T. Pompl, C. Russ, H. Gossner,
Infineon Technologies
1:50 p.m. - 2:15 p.m. Presentation A.2 – On the
Interaction Between Substrate-
Triggered ESD Protection Circuits and Embedded Parasitic Elements
Gianluca Boselli, Texas Instruments
2:15 p.m. - 2:40 p.m. Presentation A.3 – On-Chip
Protection of RF Pins
Against HMM Discharges
Guido Notermans, Dejan Maksimovic, Gerd Vermont, ST Ericsson, Zaventem Belgium;
Michiel van Maasakkers, ST Ericsson,
Nijmegen, The Netherlands; Fredrik Pusa,
Catena Wireless Electronics; Theo Smedes,
NXP Semiconductors
Poster Session 2
2:40 p.m. - 2:45 p.m. Poster Session 2 Introduction
Natarajan Mahadeva Iyer,
GLOBALFOUNDRIES
2:45 p.m. - 3:25 p.m. Poster Presentation Summaries
Poster 2.1 – Engineering Fully Silicided Large Output Driver For Maximum It1 H. Jiang, H. K. Yap, G.W. Zhang C. Wang, C. Cheng, P. R. Verma, J. Lim, M. I. Natarajan, GLOBALFOUNDRIES
Poster 2.2 – Self-Protection Capability of Integrated Power Arrays V.A. Vashchenko, D. LaFonteese, P. Hopper, National Semiconductor Corporation; M. Scholz, D. Linten, S. Thijs, P. Jansen, G. Groeseneken,IMEC
Poster 2.3 – Dual-Direction Protection in Si-Ge BiCMOS Process V.A. Vashchenko, National Semiconductor Corporation
Poster 2.4 –Transient Characterization of High Voltage Switching Devices Under ESD Stress M. Scholz, G.Vandersteen, IMEC, Vrije Universiteit Brussels, Belgium; D. Linten, IMEC; S. Thijs, M. Sawada, HANWA Electronic; G. Groeseneken, IMEC, ESAT, Katholieke Universiteit Leuven
Poster 2.5 – Development and Qualification of ESD Protection Demonstrators Using SCR Structure Compatible with Advanced CMOS Technologies Ph. Galy, C. Entringer, J. Bourgeat, F. Jezequel, B. Jacquier, A. Dray, STMicroelectronics
Poster 2.6 – Consideration of Design Window for ESD Power-Clamp in Next Generation Devices Hiroyasu Ishizuka, Yasuyuki Morishita, Takayuki Hiraoka, Kenji Hashimoto, Nobuyuki Wakai, Shigetaka Kumashiro, MIRAI-Selete Selete Sagamihara Office, NEC Sagamihara Plant
Poster 2.7 – SCR-Based Power Supply Clamp for Low Leakage Applications Kiran Chatty, Michel J. Abou-Khalil, Robert Gauthier, Semiconductor Research and Development Center, IBM Systems and Technology Group; Nathaniel Peachey, Quek Chee, RFMD
Poster 2.8 – On-Chip ESD Protection with Improved High Holding Current SCR (HHISCR) Achieving IEC 8 kV Contact System Level Bart Sorgeloos, Ilse Backers, Olivier Marichal,
Bart Keppens, Sofics
3:25 p.m. - 4:55 p.m. Poster Session 2 and Mixer (Refreshments provided)
5:00 p.m. - 6:00 p.m. Special Interest Groups
(parallel sessions)
SIG1 Two-Pin HBM Testing: Evan Grund, Grund Technical Solutions; Charvaka Duvvury, Texas Instruments
SIG2 ESD Data Analysis Software: Dimitri Linten, IMEC; David Tremouilles, LAAS-CNRS
SIG3 System-Level ESD Stress: Harald Gossner, Infineon Technologies
6:30 p.m. - 8:30 p.m. Conference DINNER
(business formal)
8:30 p.m. - 9:30 p.m. Discussion Groups (parallel sessions)
DG1 Transient Latch-up: How to Test for It? How to Design for It? Wolfgang Stadler, Infineon Technologies
DG2 ESD Qualification and ESD Control Methods:
Reinhold Gaertner, Infineon Technologies
9:30 p.m. Talk at the fireside “Are Customers Really from Mars and
the Suppliers from Venus? Find out From
the 4-year Experience of the Industry
Council”
WEDNESDAY, MAY 12
7:00 a.m. - 8:00 a.m. BREAKFAST (Dining Room)
8:00 a.m. - 8:10 a.m. Report on DG1 & DG2
8:10 a.m. - 8:15 a.m. Announcements
Technical Session B - System Level ESD Protection
8:15 a.m. - 8:50 a.m. Invited Talk 1: Future Challenges of
ESD Protection -
an Automotive OEM’s
Point of View Christian Lippert, Audi
8:50 a.m. - 9:15 a.m. Presentation B1 – Impact of a
Decoupling Capacitance
on ESD
Propagation at System Level: Full
Simulation and Measurement
Comparison N. Monnereau, F. Caignet,
D. Trémouilles, CNRS; LAAS, Université de
Toulouse, UPS, INSA, INP, ISAE, LAAS
9:15 a.m. - 9:40 a.m. Presentation B2 – Designing the System
Level ESD Protection
Against IEC
61000-4-2 Stress with TLP Data and SPICE Simulation Liafang Lou, Charvaka Duvvury, Agha Jahanzeb, Texas Instruments
9:40 a.m. - 10:05 a.m. Presentation B3 – IC Characterization
for ESD System:
Is the Human
Metal Model the Right Approach?
Wolfgang Stadler, Tilo Brodbeck, Josef
Niemesheim, Reinhold Gaertner, Harald Gossner,
Werner Simbuerger, David Johnsson, Matthias
Stecher, Yiqun Cao, Infineon Technologies
Poster Session 3
10:05 a.m. - 10:10 a.m. Poster Session 3 Introduction
Natarajan Mahadeva Iyer, GLOBALFOUNDRIES
10:10 a.m. - 10:45 a.m. Poster Presentation Summaries
Poster 3.1 – EDA Tool for Checking Signal Power Domain Crossings Melanie Etherton, Michael Khazhinsky, Edgar Oropeza, Eliseo Torres, Suzanne Biganzoli, Freescale Semiconductor; Steffen Lorenz, Louis Thiam, Cadence Design Systems
Poster 3.2 – Simple IC’s-Internal-Protection Models for System Level ESD Simulation D. Trémouilles, N. Monnereau, F. Caignet, M. Bafleur, CNRS; LAAS, Université de Toulouse; UPS, INSA, INP, ISAE; LAAS
Poster 3.3 – System to Component Level Correlation Factor S. Thijs, D. Linten, IMEC vzw; M. Scholz, IMEC, Vrije Universiteit Brussels; C. Russ, W.Stadler, Infineon Technologies; M. Sawada, HANWA Electronics Ind. Co. Ltd.; G. Groeseneken, IMEC, Katholieke Universiteit Leuven
Poster 3.4 – A Case Study of System Level ESD Protection Agha Jahanzeb, Lifang Lou, Charvaka Duvvury, Scott Morrison, Texas Instruments
Poster 3.5 – Invasive System Level ESD Current Measurement Using Magnetic Field Probe Fabrice Caignet, Nicolas Monnereau, Nicolas Nolhier, LAAS-CNRS
Poster 3.6 – ESD/EOS Validation of Electrical Components Pasi Tamminen, NOKIA Corporation; Toni Viheriakoski, Cascade Metrology
Poster 3.7 – ESD Robustness Verification for System-on-a-Chip Designs Pritesh Johari, Youlin Liao, Norman Chang, Aveek Sarkar, Apache Design Solutions
10:45 a.m. - 12:00 p.m. Poster Session 3 (Refreshments provided)
12:00 p.m. - 1:00 p.m. LUNCH (Dining Room)
1:00 p.m. - 5:30 p.m. FREE TIME - The afternoon is free
for discussion
or to enjoy outdoor recreation.
5:30 p.m. - 6:30 p.m. Special Interest Groups
(parallel sessions)
SIG4 Transient Latch-up (TLU): Wolfgang Stadler, Infineon Technologies
SIG5 ESD EDA Tools: Michael Khazhinsky, Freescale, Vesselin Vassilev, Novorell
6:30 p.m. - 8:00 p.m. DINNER (Dining Room)
8:00 p.m. - 9:00 p.m. Discussion Groups (parallel sessions)
DG3 Automotive System ESD Protection:
Markus Mergens, QPX
DG4 How Useful and Reliable are TLP Tools?
Leo G. Henry, ESD & TLP Consultants
9:00 p.m. - 10:00 p.m. Open Poster Session
THURSDAY, MAY 13
7:00 a.m. - 8:00 a.m. BREAKFAST (Dining Room)
8:00 a.m. - 8:10 a.m. Report on DG3 & DG4
8:10 a.m. - 8:15 a.m. Announcements
Technical Session C&D - Transient Behavior and CDM Effects
8:15 a.m. - 9:00 a.m. Invited Talk 2 - IC Package
Technology Advancements &
Challenges for this Decade Mahadevan Iyer, Texas Instruments
9:00 a.m. - 9:25 a.m. Presentation C.1– Impact of Voltage
Overshoots on ESD
Protection
Effectiveness for High Voltage
Applications Yiqun Cao, Infineon
Technologies, Technische Univsität Dortmund;
Ulrich Glaser, Alevtina Podgaynaya, Joost Willemen,
Matthias Stecher, Infineon Technologies; Stephan
Frei, Technische Universität Dortmund
9:25 a.m. - 9:50 a.m. Presentation C.2 – Cross Domain
Protection Analysis and
Verification Using
Whole Chip ESD Simulation Mototsugu
Okushima, Tomohiro Kitayama, Susumu Kobayashi,
Tetsuya Kato, Morihisa Hirata, NEC Electronics
Corporation
9:50 a.m. - 10:15 a.m. Presentation C.3 – CDM2 – A New CDM
Test Method for
Improved Test
Repeatability and Reproducibility Robert
Given, Marcos Hernandez, Tom Meuse, Thermo
Fisher Scientific
10:15 a.m. - 10:35 a.m. BREAK (Refreshments Provided)
10:35 a.m. - 11:00 a.m. Presentation D.1– Pulse Risetime Effect
on Current
Filamentary Modes and
Interaction of Current Filaments in
ESD Protection Devices W. Mamanee, S.
Bychikhin, E. Gornik, D. Pogany, Vienna
University of Technology; D. Johnsson, M. Stecher,
H. Gossner, Infineon Technologies; P. Rodin,
Ioffe Physicotechnical Institute
11:00 a.m. - 11:25 a.m. Presentation D.2– Influence of
Geometrical Parameters
on Time-to-
Latch-Up of SCR-Based ESD Protection
Structures Augusto Tazzoli, Gaudenzio
Meneghesso, University of Padova; Martina
Cordoni, Paolo Colombo, STMicroelectronics
11:25 a.m. - 11:50 a.m. Invited Talk 3 - Simulation Based
Analysis of ESD
Protection Elements
on Systemlevel, Best Paper of ESD
Forum 2009 Bastian Arndt, Continental
Automotive
11:50 a.m. - 12:20 p.m. Special Interest Group Reports
12:20 p.m. - 12:25 p.m. IEW 2011 Announcement
12:25 p.m. - 12:40 p.m. Closing Remarks
12:40 p.m. - 1:30 p.m. LUNCH (Dining Room)
DEPART
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