Seminars give an overview of technology challanges!
Seminar Chair: Horst Gieser, Fraunhofer IZM
This group of seminars cover four closely connected topics. CDM and alternative characterization methods in the sub nanosecond regime are extremely helpful tools to analyze the protection capability in modern ICs. However, the results have to be carefully checked to avoid misinterpretation. To protect a system against malfunction during IEC discharge, very fast rising pulses with high energies need to be considered. EMC design methods largely determine how much the IC pin is affected. The implemented protection is often in competition with the performance requirements of a system, especially for RF and broadband interfaces. Meanwhile, methods are in place which provide a good solution for both high speed performance and ESD robustness. Finally, most modern communication systems are realized in very advanced CMOS technologies. This adds an additional challenge to ESD protection design and clearly limits the achievable robustness level of an on-chip protection for CDM like stress.
CDM Charged Device Model Test: Current Status and Possible Alternatives
Heinrich Wolf, Fraunhofer IZM
In a modern production environment the Charged Device Model (CDM) becomes more and more relevant concerning ESD failures of product ICs. Furthermore, the ESD design window is shrinking for modern ultra deep submicron technologies. This requires test methods with high accuracy and reproducibility. The current CDM standards allow for a high variation of the peak current value for a given pre-charge voltage. Mainly, the uncontrolled air discharge spark during a CDM stress introduces this lack in reproducibility and accuracy of the obtained failure thresholds. JEDEC and ESDA aim to merge their standards into one. Recently, new CDM-like test methods have been developed which should achieve more reliable test results. After a review of the current CDM status, including White Paper 2 of the Industry Council, this seminar will discuss and compare the different test methods.
ESD/EMC in an Automotive Environment
Patrice Besse, Freescale
ESD ruggedness is part of IC specifications and it is currently evaluated by well known stresses (CDM, MM, HBM). From a system point of view, the ESD robustness should guarantee safe operation if an ESD event appears while the product is functioning or not. For automotive, OEMs and car makers consider ESD an electromagnetic disturbance and it is usually part of a global electromagnetic compatibility (EMC) specification. IEC and ISO standards define the test procedures, but car makers also require specific ESD tests. For embedded system ESD and EMC, tests are achieved on cables and connectors of the Electronic Control Unit and a large part of the stress is withstood by the IC itself. ESD and EMC strategies have to be compatible at both the IC and system levels. As we will see on several products, external devices are often added to improve the ESD/EMC performances, but in some cases it does not help and can decrease the robustness. This seminar will discuss the common and specific ESD/EMC system requirements we need to take into account at the die level. An integrated ESD protection dedicated to the system level stresses will be presented as an example.
ESD-Protection of Advanced RF and Broadband Integrated Circuits and MEMS
Dimitri Linten, IMEC
Today’s RF applications reach higher operating frequencies than before, with a larger available bandwidth. Developing a successful ESD protection methodology for the RF IO pins requires both RF and ESD design skills. During the last decade, several RF ESD protection methodologies have been presented in literature. This seminar will classify the available techniques and present an overview on the state-of-the-art ESD solutions for both narrowband and wideband RF and mm-wave applications.
Additionally, in the recent year MEMS switching devices have been introduced into these applications. The study of the reliability and failure mechanisms of MEMS under ESD stress has therefore received increasing attention. Next to the ESD characterization of the MEMS, providing ESD solutions for ICs with integrated MEMS is currently a key challenge.
ESD-Aspects of FinFETs and other Most Advanced Devices
Christian Russ, Infineon Technologies
The 28 nm and 22 nm CMOS technology nodes are already posing many ESD challenges on technology, device and circuit level. However, the main question still lies ahead of us: Will there be a fundamental change in device architecture to enable downscaling towards 16 nm? Planar bulk CMOS is still successfully pushing its own limits and the big disruption is still to come. But the race between classical CMOS bulk and novel 3-D device geometries such as FinFETs is already on! Obviously, ESD protection design must not be a show-stopper. Whatever the scenario will be – classical bulk CMOS or 3-D devices - we better get prepared!
We give an overview on the ESD performance of IC technologies that are close to industrial production or which have good chances because of their proven ability for large scale integration. We compare advanced ESD devices in FinFET technology - on SOI and bulk substrate - with planar CMOS devices. We will assess process features introduced to push CMOS further, such as strained silicon or HighK dielectrics. Characterization data and failure mechanisms will help to judge voltage clamping, thermal properties, and turn-on speed of the devices, in view of their suitability for ESD protection, such as for hyper thin gate dielectrics and various voltages for supply or signaling.
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